module pc(
    input clk,
    input reset,
    input [5:0] stall,
    input [63:0] i_inst_addr,
    input [63:0] new_pc,
    input flush,
    input ret,

    output reg [63:0] o_inst_addr,
    output [63:0] o_badvaddr,
    output [63:0] o_excode,
    output o_except_ena
);

    always @(posedge clk) begin
        if(reset) begin
            o_inst_addr <= 64'h0000000080000000 - 4;
        end else if(flush | ret) begin
            o_inst_addr <= new_pc;
        end else if(stall[0] == 1'b0) begin
            o_inst_addr <= i_inst_addr;
        end
    end

    assign o_badvaddr = i_inst_addr[1:0] == 2'b00 ? 64'd0 : i_inst_addr;
    assign o_excode = i_inst_addr[1:0] == 2'b00 ? 64'd0 : {1'b0, 63'd0};
    assign o_except_ena = i_inst_addr[1:0] == 2'b00 ? 1'b0 : 1'b1;

endmodule
